To keep pace with market demand for more performance and functionality in today’s mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip’s transistors and other physical features can be smaller than the wavelength of light used to print them.
Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.
Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.
New Allegro 16.5 Technology:
The latest Allegro technology will be available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB
designers benefits such as:
- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through “base plus options” configurations Fixed in Cadence SPB OrCAD 16.5.010:
CCRID PRODUCT PRODUCTLEVEL2 TITLE
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
941499 ALLEGRO_EDITOR DRAFTING BUG:Limit Tolerance isnot working for Dimensioning
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
942914 SIG_INTEGRITY OTHER ZAxis delay calculation
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
946819 SIP_LAYOUT DEGASSING Shape degass command
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
DATE: 10-26-2011 HOTFIX VERSION: 009