HDL Works IO Checker v2.1 R1 | 26 Mb
Verifying hundreds of FPGA IO pins between PCB and FPGA in minutes - When using large FPGA's on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task. On the FPGA side the pins are assigned to the HDL signals that form the toplevel of the logic implemented on the FPGA. On the PCB side the pins have to be connected to the proper net that will connect it to other components on the PCB.
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